In the integrated circuit it is well known that input/output (I/O) pad acts as a bridge communicating one chip between another. Specifically, the I/O pad function as a buffer, as shown in FIG. 1a, with input terminal A and output terminal Z. The buffer's operation is, for example, imposing a signal on terminal A, and a signal having the same pulse width will appear on terminal Z with a delay of several neon-seconds. So the I/O pad dose not perform filtering.
As shown in FIG. 1b, a capacitor C is coupled in-between to an inverter set including two series connected inverters, the inverter set has an input terminal A, an output terminal Z. The terminal voltage of the capacitor C to ground is denoted as VCP, the voltage on terminal A is VA, and the voltage at terminal Z is VZ. It tends to malfunction if coupling the I/O pad to a low pass element to filter output signal. For example, if the device (including the capacitor C and the inverter set) in FIG. 1b is designed to filter the pulse having pulse width smaller than 20 ns (nano-seconds), it is inclined to malfunction due to the situation described below. After the pulse H1, having pulse width 15 ns, has passed through the first inverter INV1, the capacitor C is charged to VCP, however, VCP dose not reach the threshold voltage VTH of the second inverter INV2, so the voltage on the output terminal remains unchanged (equal to 0), and the pulse H1 had been filtered at this time. Subsequently, VA returns to its' original level (e.g. 0) for a time duration L (e.g. 5 ns), and then the capacitor C, within time duration L, discharges through the first inverter INV1. If the capacitor C is not completely discharged within time duration L, and a second pulse H2 following L is applied on terminal A, the terminal voltage VCP of capacitor C starts to rise before it return to 0, so VCP tends to reaches VTH even if the pulse of the input pulse H2 is smaller than 20 ns. Thus the voltage VZ on the output terminal Z reaches a certain level other than its' original one (0), however, it is expected that, as long as the pulse width of the input pulse H2 is smaller than 20 ns, the output voltage VZ should remain unchanged. In other words, the low pass characteristic of the device in FIG. 1b (including inverter INV1 connected to capacitor C and inverter INV2) disappeared due to the residual charges on capacitor C, which relates to the time duration L between input pulse H1 and pulse H2. Take the time duration L as 5 ns as an example, as shown in FIG. 1b, while the rear half (around 10 ns) of pulse H2 starts to be applied on terminal A, because VCP begin to exceeds VTH (VCP>VTH), a signal expected to be filtered, unexpectedly appears at the output terminal Z.
Due to the disadvantages mentioned above, the improvement can be made by a circuit which utilizes feed back signal to reset timing pulse, and uses MOS (Metal-Oxide-Semiconductor) transistor to enable large current drivability. Thus the fast charging/discharging operation is made possible, and the problems resulted from residual charges is being prevented.